The influence of the substrate material on the column and grain microstructure, the residual stresses, crack patterns and delamination of Cr films has been investigated using TEM, SEM, and X-ray diffraction. The inter-influence of these factors which determine the long term reliability of microelectronics is discussed. When interfacial adhesion is very low, as may be the case with some polymer substrates, cracking occurs discontinuously during film formation each time the stress exceeds the critical value for fracture.

Bismuth oxide has been found to be a useful flux for the preparation of dense body cordierite (Mg2Al4Si5O18). The use of as little as 2 atom% bismuth ion with the appropriate mixture of commercially available oxide starting materials serves to produce fully dense crystalline cordierite after firing at 1000 °C. The microstructure of the sintered body (92 w/o% cordierite, 8 w/o% bismuth oxide) has the residual bismuth oxide flux distributed in discontinuous domains at the grain boundaries and at the triple points. Physical properties such as thermal coefficient of expansion and dielectric constant are largely unperturbed by the presence of the flux.

Green tapes having high volume fraction solids loading have been fabricated from bismuth oxide-cordierite precursor powders. The subsequent firing at 1000 °C of laminated green tapes yields fully dense ceramic bodies of crystalline cordierite.

Insulating polymeric sheets were made electrically conductive by ion implantation. The effects of implantation parameters, such as ion species, dose, energy, beam current density, and substrate temperature, on the resultant sheet resistivities were investigated. Surface structural changes of implanted polymers were evaluated by X-ray photoelectron spectroscopy (XPS), Rutherford backscattering spectroscopy (RBS), and Fourier transform infared spectroscopy (FTIR). Electron spin resonance (ESR) and temperature dependent resistivity measurements were performed to explore the conduction mechanisms of implanted polymers. The results indicate that ion beam modification of polymers proceeds via a similar mechanism as high temperature pyrolysis. The resultant carbon-enriched materials which can be described by the conducting grain model.

An x-ray photoelectron spectroscopy (XPS) study of laser treated and heat treated Kapton®indicates that both the treatments result in depleting the carbonyl groups from the sample and leave behind a conducting residue that still contains significant amounts of oxygen and nitrogen. The rapid changes in surface composition coincide with a substantial decrease in the electrical resistivity of the polyimide samples.

Mullite ceramics were developed for multilayered packages, which have a lower dielectric constant and a nearer thermal expansion to that of silicon than those of alumina. The multilayered mullite packages are manufactured by using a similar cofired technology with tungsten or molybdenum to the conventionally used alumina system. A new brazing material and a new lead material were developed to be combined with the mullite ceramics Multilayered mullite packages with a brazed aluminum nitride heat sink, which has a high thermal conductivity, were developed to compensate a low thermal conductivity of the mullite itself. The packages are one of the highest performance packages.

A broad review of ceramics in microelectronics for processing, storing, transferring, printing, and displaying information is highlighted. Ceramic packaging is presented with a review of the history, evolution, and state of the art. The recent developments in ceramics resulting in potentially improved thermal and electrical properties by the use of SiC, AIN, and glass±ceramics are discussed. The scientific understanding necessary to support these developments is mentioned.

Polymeric materials have traditionally enjoyed widespread use in the electronics industry. Recent advances in the identification and synthesis of polymers with unusual electrical and optical properties have opened new opportunities for technological applications. Some of these novel properties are summarized in this paper with an emphasis on how these properties may be usefully exploited in the area of multichip packaging.

Materials problems have always been a significant cause of wire bond failures in microelectronics. However, modern VLSI materials, processing, and packaging methods combined often result in new or masked versions of old failure mechanisms. This paper describes the classical Au-Al intermetallic compound problem as described by a new two-dimensional finite element diffusion model and demonstrates that diffusion in poor welds is more rapid than in bulk couples. Failures resulting from modern bonding material couples (e.g., Cu-Au, Al-Ag, etc.) can result in bond failures superficially resembling Au-Al type failures. Failures resulting from bonds made to contaminated gold electroplated films are described, and a new failure model resulting from hydrogen in these films is shown.

In relation to other surface mounting methods for bare integrated circuits, Flipped Direct Chip Attachment (FDCA) provides the most compact level-1 interconnection. High performance adhesives represent an interesting alternative to solders and conductive pastes, which are now being used for FDCA interconnections. These materials may provide the ability to achieve higher interconnection density on a larger chip and at the same time provide encapsulation of the active face of the chip. They may also provide simpler and cleaner manufacturing processes, resulting in lower installed costs.

The purpose of this paper is to describe recent findings that are relevant to the question of whether FDCA with adhesives is a viable concept. Experimental results are reported that provide a description of the characteristics of pressure engaged interconnections that were obtained using a proprietary structural adhesive system. In addition, results of a thermomechanical modeling study are reported that provide estimates of the thermal stress distribution in an FDCA adhesive bond.

This paper will report on a novel photolithographic process suitable for the fabrication of gold bumps on high lead count devices. Utilizing a photosensitive polyimide, straight wall bumps are grown completely recessed within the polyimide layer to a typical height of 25 microns.

The photolithographic step of the bumping process will be described. Good layer uniformity in conjunction with exposure in vacuum hard contact mode leads to practically vertical walls of the opening in the polyimide layer after develop.

Straight wall gold bumps have been electroplated in 30 micron wide openings with a 50 micron centerline spacing. This density is beyond the present spacing capability of TAB in production. The bumping process is no longer the limiting factor in high lead count device fabrication.

Potential residues in the polyimide openings would result in bad bump adhesion strength and high bump contact resistance to the underlying metallization. These two parameters were used for the process optimization.

An in-depth review of controlled collapse chip connections (c-4), or otherwise known as Flip Chip Solder Joining Technology, is present. The C4 joint utilizes solder bumps deposited on wettable terminals on the chip and a matching footprint of the substrate. The upsidedown chip (flip chip) is aligned to the substrate and all joints are made simultaneously by reflowing the solder. An in depth review of this technology is presented. Materials, design factors, fabrication processes, tools, assembly, rework, and reliability are discussed. Future trends are indicated and comparisons make with wire bonding and Tab (tape automated bonding).

The fatigue of solder joints is a dominant factor limiting the long term reliability of electrical devices, especially when modern surface mounting is employed to attach devices to wiring boards. This paper will review the critical variables which determine the fatigue of solder and solder interconnections for the joints encountered with surface mounted devices. Consideration will first be given to the variables determining the displacement that a joint experiences due to an imposed thermal cycle. This displacement will then be related to strains in the joint. These strains are then correlated to the fatigue life. This final correlation requires not only a knowledge of the magnitude of the strain which is being applied, but also nature of the joint geometry, type of solder employed, stress state, the definition of failure, the frequency of fatigue cycling, the introduction of hold times, the environment (both thermal and gaseous) and the occurrence of metallurgical changes. The importance of these critical variables will be discussed along with an outline of design approaches to predict the fatigue life. Data for tests on eutectic Pb-Sn solder and for a Pb rich solder will be presented and used to illustrate the influence of critical variables on the fatigue life and to illustrate design approaches.

A critical investigation of the use of the wetting balance to characterize leadfinish solderability is described. The wetting force vs. time curves for matte tin and solder plated copper coupons which have been subjected to well controlled environmental conditions, such as steam and high temperature bakes have been analyzed. Steam exposure was shown to impact greatly the shape of the wetting force curve, with the major effect observed after one hour of exposure and with no significant changes upon further exposure. The high temperature exposure (bake) and associated intermetallic compound formation had little effect on the force-time curve as long as it was protected from oxidation. Results show that when the wetting balance is used in conjunction with SEM and microanalysis tools, it is an excellent diagnostic tool for determining sources of solderability changes.

Thermal management in the packaging of electronic components is fast becoming an enabling technology in the development of reliable electronics for a range of applications. The objective of the paper is to assess the feasibility of using advance high thermal conductivity pitch fiber (HTCPF) as a solution to some of the packaging problems. The general scope will include the following: identification of the candidate material and its potential applications; thermal management of the chip to board interface; thermal management of the heat within the multi-layer interconnect board (MIB); thermal management of the standard electronic module-format E (SEME); and heat transfer thru the enclosure to a remote heatsink/heat exchanger.

A model to characterize the development of thermal stresses in printed wiring board (PWB)-mounted multilayer ceramic capacitors (MLCC's) is presented. The model is developed analytically using uncoupled, quasi-static thermoelastic theory. Both the actual 2D geometry and mechanical and thermal properties of real MLCC-PWB structures are incorporated in the model. A particular method for solving the model equations is presented and implemented. Preliminary numerical results indicate that the values and spatial patterns of stress are in agreement with data available in the experimental literature.

Microchemical and microstructural study has been carried out on the tungsten-aluminum nitride (W-AlN) thick film metallization interface. A reaction has been found to occur with the formation of precipitates at AlN grain boundaries and also within the AlN grains; a thin crystalline grain boundary film was also observed. The interface morphology and chemistry is compared to the molybdenum/manganese-aluminum nitride (MoMn-AlN) interface. The effects of morphology and microchemical variations upon thermal conductivity are discussed.