This book is about primary science education. It presents the latest evidence-informed ideas, strategies, resources and information for your consideration as you build your knowledge and expertise as a teacher in this foundational learning area. Underpinned by the premise of building your own and your students’ science identity, there is a focus on learning through using local outdoor areas, socio-scientific issues and current events as stimuli for questions and investigations to better understand how science is practised in the real world, and that it is a ‘messy’ human endeavour – particularly when it comes to solving real-world issues. Each chapter and its sections respond to questions about why we teach science in primary school, how students can demonstrate their learning, how to plan effective lessons and learning sequences, the teacher’s role in a primary science classroom, how the integration of other learning areas and cross-curriculum priorities can be used to support the learning of science concepts when there are compelling synergistic links, and much more.

In this chapter we will discuss another non-linear data structure: graph. We have already discussed a non-linear data structure, tree, where we found the hierarchical relation among nodes. Every parent node may have zero or more child nodes, i.e. the relationship is one-to-many. In graph, we will find that every node may be connected to any node, i.e. the relationship is many-to-many. Here we will discuss various terms related to a graph and then its representation in memory. We will also discuss the operations on a graph as well as its different applications.

12.1 Definition and Concept

A graph is a very important non-linear data structure in computer science. A graph is a non-linear data structure that basically consists of some vertices and edges. We can define a graph, G, as an ordered set of vertices and edges, i.e. G = {v, e}, where v represents the set of vertices, which is also called nodes, and e represents the edges, i.e. the connectors between the vertices. Figure 12.1 shows a graph where the vertex set v = {v1, v2, v3, v4, v5, v6} and the edge set e = {e1, e2, e3, e4, e5, e6, e7, e8, e9}, i.e. the graph has 6 vertices and 9 edges.

12.2 Terminology

In this section we will discuss the various terms related to graphs.

Directed graph: If the edges of a graph are associated with some directions, the graph is known as a directed graph or digraph. If the direction of an edge is from vi to vj, it means we can traverse the nodes from vi to vj but not from vj to vi. An edge may contain directions in both sides. Then we may traverse from vi to vj as well as from vj to vi. Figure 12.2 shows a directed graph.

Undirected graph: When there is no direction associated with an edge, the graph is known as undirected graph. In case of undirected graph, if there is an edge between the vertex vi and vj, the graph can be traversed in both directions, i.e. from vi to vj as well as from vj to vi. The graph shown in Figure 12.1 is an undirected graph.

The fundamental theories and principles related to digital systems, such as the number systems, codes and the Boolean algebra are discussed in Chapter 13. This chapter presents the practical enactments of those concepts with digital electronic circuits. The basic logic gates, namely AND, OR and NOT and universal gates (NAND and NOR) are illustrated and the working principles of the following types of digital circuits based on the combinations of these gates are explained.

The different categories of combinations of electronic components for realizing logic gates, known as logic families are also introduced.

Boolean Algebra and Digital Electronics

The algebraic expressions involving Boolean variables (Chapter 13) and their practical realization in terms of voltage levels associated with electronic circuits are two different but interrelated subjects. Boolean algebra is a mathematical theory involving two-state variables and their combinations whereas digital electronics realizes those variables and their algebraic operations in terms of electrical signals of two distinct levels.

English mathematician George Boole (1815–1864) propounded (1854) several symbolic logical expressions involving two states only. The possibility of its practical application was first realized when American engineer Claude E. Shannon (1916–2001) applied (1938) such concept to the analysis of telephone switching circuits, the ‘closed’ and ‘open’ conditions of relay switches being indicated by the two states of Boolean logic. This was the pioneering work on the application of Boolean algebra to digital electronics. Then it got further maturity with the contributions of Karnaugh, De Morgan, and other notable scientists.

A digital electronic circuit is constructed with our known elements, such as diodes, transistors, and FETs along with resistors and capacitors. The difference is that the digital circuits operate with only two discrete levels of voltage for inputs and outputs representing the two possible states of Boolean variables. Digital electronics deals with circuits performing mainly the following operations.

Arithmetic and Logic Operations: An adder circuit can execute binary addition, binary subtraction as negative addition, binary multiplication as repeated addition, and binary division as repeated negative addition. A comparator circuit can decide whether a given binary number is greater than, equal to or less than another.

Thus far, we have discussed the dynamics and response characteristics of various physical systems. In doing so, we have developed many useful modeling and analysis techniques that help us to understand the behavior of first-, second-, and higher-order dynamic systems. One important application of these tools is to design systems that meet certain requirements or criteria in the responses of their output variables, such as the settling time and final value of a motor’s velocity in response to a step input.

Test patterns enable testers to distinguish between a faulty circuit and a fault-free circuit. A test pattern is a bit sequence that we can apply at the input ports such that we are able to observe different responses for a faulty circuit and a fault-free circuit. In general, it is difficult to find a test pattern for a given fault manually. Therefore, given a fault model, we generate test patterns for a circuit using some electronic design automation (EDA) tools. The process of automatically finding a set of test patterns is called automatic test pattern generation (ATPG). In this chapter, we will discuss ATPG in detail.

REQUIREMENTS OF ATPG

In Chapter 21 (“Scan design”), we have seen that a given fault of a circuit can be detected using multiple test patterns. Moreover, a given test pattern can detect multiple faults in a circuit. Therefore, given a circuit and a set of faults, different ATPG tools can generate a different set of test patterns. We expect that a good ATPG tool will fulfill the following requirements:

• 1. Achieves a high fault coverage: As the fault coverage increases, the quality of testing improves, and the defect level decreases. Therefore, the set of test patterns generated by an ATPG tool should ideally cover all (100%) detectable faults for a given fault model. In practice, 98% –100% fault coverage is typically acceptable.

• 2. Generates a small test pattern set: The set of test patterns generated by an ATPG tool is applied to the device under test (DUT) using an automatic test equipment (ATE). Typically, test patterns and their responses are stored in the memory of the ATE and applied to the DUT during testing through some tester channels. For scan-based design, the test application time is directly proportional to the test set size. Therefore, to reduce the recurring cost of testing,

Describes the rationale for, and approach to, regulation of the aviation industry. Considers the effects of restructuring, airline alliances, and the future regulation of unmanned aircraft

This chapter complements Chapter 5 in Government Accountability: Australian Administrative Law, third edition, which investigates the role of parliament and other bodies, such as auditors-general and ombudsmen, in scrutinising and investigating the actions of government.

One occasionally encounters the misconception that two-component spinor notation is somehow inherently ill-suited or unwieldy for practical use. Perhaps this is due in part to a lack of examples of calculations using two-component language in the pedagogical literature. In this chapter, we seek to dispel this idea by presenting Feynman rules for external fermions using two-component spinor notation, intended for practical calculations of cross sections, decays, and radiative corrections.

Consider a collection of $N$ two-component left-handed $(\frac{1}{2},0)$ fermions. The corresponding free-field Lagrangian is invariant under a global $\text{U}\left(N\right)$ symmetry. When a mass term and interactions are added to the theory, the global $\text{U}\left(N\right)$ symmetry is broken down to a discrete ${\mathbb{Z}}_2$ symmetry that reflects the fact that any term in the Lagrangian must contain an even number of fermion fields.

This chapter complements Chapter 3 in Government Accountability: Australian Administrative Law, third edition, which investigates the various classes of executive power, both statutory and non-statutory. The vast majority of executive power is conferred by statute. The extracts emphasise the importance of statutory interpretation when establishing the scope of express and implied powers. The final two extracts consider prerogative power.

In Chapter 1, we focused on quantum field theories of free fermions. In order to construct renormalizable interacting quantum field theories, we must introduce additional fields. The requirement of renormalizability imposes two constraints. First, the couplings in the interaction Lagrangian must have nonnegative mass dimension.

This chapter complements Chapter 7 of Government Accountability: Australia Administrative Law, third edition. An important point is that merits review is a creature of statute. The availability of merits review, the authority responsible for conducting review, the nature of review, the process to be followed and the remedies available in a given case can only be determined by careful examination of the relevant statutory provisions. For this reason, this chapter is not a collection of canonical authorities on merits review; few, if any, such authorities exist. The first two sections of this chapter provide government perspectives on the need for, aims of, and potential drawbacks of, merits review. The third section consists of two case studies of merits review. These cases are chosen to show how a merits review application might proceed; how merits review arguments are constructed; and the possible outcomes of merits review.