This chapter presents foundational ideas and discussion around the notion of worldviews, including how they develop, how they are influenced by education and how they impact learning. There is a focus on identifying the features of worldviews that incorporate science perspectives with an emphasis on strategies for nurturing and developing students’ scientific dispositions, such as their ‘science identity’ and ‘science capital’. The contributing role of primary science education through the Australian Curriculum will be examined. As we work through these ideas, you will examine your own worldviews about science and use evidence from the science education research literature to explore current views about the purposes of science education in primary schools.

In a synchronous circuit, the clock signal synchronizes the operation of various circuit elements. For deterministic circuit operation, certain timing constraints must be satisfied between the data signal relative to the clock signal. If these constraints are violated then the circuit can go into a metastable state or an invalid state. Therefore, we need to verify that these constraints are indeed satisfied in a synchronous circuit [1–4]. We use static timing analysis (STA) for this purpose. The simplicity and computational efficiency of STA have made synchronous design methodology the de facto standard for complicated digital circuits.

An STA tool verifies that a given synchronous circuit operates deterministically and remains in a valid state for a given frequency even in the worst-case scenario. Note that the purpose of STA is not to find a frequency at which a circuit can operate. Its purpose is just to ascertain whether a given circuit can safely operate at a given frequency and operating conditions. Therefore, STA needs to examine only the worst-case behavior for the circuit. It greatly simplifies the problem for an STA tool. It need not evaluate the circuit response to all possible input stimuli because most of them do not contribute to the worst-case behavior. Hence, STA employs methods that do not require applying stimuli and observing their dynamic responses. In this sense, STA is a static verification technique. It employs efficient stimuli-independent techniques to examine the worst-case behavior of a circuit.

In this chapter, we first describe the expected behavior of a synchronous circuit. Then, we derive the timing constraints that must be met to achieve this synchronous behavior. Next, we explain the techniques employed by the STA tools to ensure that these constraints are satisfied. We also highlight the assumptions used by the STA tools and point out the merits and demerits of these assumptions. Finally, we explain some of the popular techniques to account for variations in STA.

The power–performance trade-off has now become a key ingredient in VLSI design flows. The increased power dissipation in integrated circuits (ICs) and the ubiquitous use of battery-powered devices have made incorporating power-saving techniques essential to the design flows. Since powersaving strategies are more effective early in the flow, we adopt low-power design methodologies right from the pre-RTL stages. Subsequently, the power-related tasks permeate throughout the design flow.

We can broadly classify the power-related tasks as: power analysis and power-driven optimizations. In this chapter, we will explain power analysis methods. In the next chapter (“Powerdriven optimization”), we will discuss power optimization techniques.

COMPONENTS OF POWER DISSIPATION

There are two components of power dissipation in a CMOS circuit: dynamic power dissipation and static power dissipation. The dynamic power dissipation occurs when a circuit performs computation actively, i.e., a signal or the output of a logic gate changes its value. The static power dissipation occurs when the circuit is powered on (supply voltages are applied), but it does not perform active computation. Let us understand these components of power dissipation in more detail.

Dynamic Power Dissipation

Consider a CMOS inverter II, shown in Figure 18.1(a). The output pin drives the input of other logic gates through wires. The total load due to these M input pins is CI = ΣM i=1 Ci, where Ci is the capacitance of the ith input pin. The wires offer load capacitance Cw. Additionally, the driving pin Z has parasitic capacitances Cd due to the drain diffusion regions of the transistors. Thus, an output pin of a CMOS logic gate has total load capacitance:

We can use the circuit shown in Figure 18.1(b) for understanding dynamic power dissipation. Assume that the inverter undergoes a transition from 0→1 or 1→0. These transitions lead to power dissipation due to switching of capacitors and due to drawing short-circuit current from the power supply. We discuss these components of power dissipation in the following paragraphs.

Another important data structure is queue. Queues are also exhaustively used in various situations in computer science. In this chapter we will discuss the operations related to queues; how a queue is represented in memory, both array and linked representation of queues, different types of queues and various applications of queues.

9.1 Definitions and Concept

A queue is a linear data structure in which insertion and deletion operations take place at two different ends. The insertion operation is commonly known as ENQUEUE and the deletion operation is known as DEQUEUE. These two operations take place at two different ends. The end at which elements are inserted is known as the rear end and the other end at which elements are deleted from the queue is known as the front end. Elements are inserted through the rear end and removed through the front end following the First-In-First-Out (FIFO) order, i.e. in the order the elements entered the queue they will leave the queue maintaining the same order. In real life we are very familiar with queues. We can see several queues in our surroundings. For example, passengers standing in front of a railway ticket booking counter. The passenger who stands at the first position gets the ticket first and when a new passenger comes, he joins the queue at the end. The same can be seen when passengers wait at a bus stop, people standing in front of a ticket counter in a cinema hall, luggage moving through conveyor belt, cars passing through single lane in a one-way road, etc.

9.2 Operations Associated with Queues

The basic operations related to a queue are as follows:

• • Enqueue: Insert an element into a queue.

• • Dequeue: Retrieve an element from a queue.

Apart from these basic two operations, to use a queue efficiently we need to add the following functionalities:

• • Peek: Get the front element of a queue without removing it.

• • Isempty: To check whether a queue is empty or not.

• • Isfull: To check whether a queue is full or not.

All these operations execute with the time complexity O(1).

Like in stack, the peek operation is required to check the front element of the queue without removing it. And if a queue is full, the enqueue operation cannot be done on the queue. Similarly, dequeue and peek operations cannot be performed on an empty queue.

Following our discussions in Ch. 5 on developing analytical and numerical solutions of system responses, Ch. 6 is focused on critical features of these solutions, known as , for systems with responses that do not tend to infinity when excited by a pulse input. The primary characteristics of these responses include the settling time, the percent overshoot, and the frequency of oscillations (i.e., if they exist), all of which can be obtained analytically, numerically, or experimentally using simple test inputs – such as steps or sinusoids. Once the response characteristics are established for a test input, the implications for more complex excitations can be understood by applying the concept of superposition (see Sec. 1.3) for linear systems.

This chapter presents illustrated examples of successful units of work designed and implemented by experienced teachers for a range of topics and ties together ideas from Chapters 2 (curriculum requirements), 3 (assessment), 4 (lesson sequencing) and 5 (teacher role). These units are considered to be successful because they address required, relevant aspects of the science curriculum; each has been implemented in primary school classrooms with students; those students have been engaged and interested in the related scientific concepts; and all students have demonstrated evidence of learning resulting from the designed experiences.

Recursion is a very important concept in programming technique. In programming there are situations where we may find that the solution of a problem can be achieved by solving smaller instances of that same problem. For example, in tree data structure, all the properties that comprise a tree also feature in its sub-trees. So, to get a solution for the tree first we need to get the solution of its sub-trees. Again to get the solution of a sub-tree we need to get the solution of the sub-trees of this sub-tree, and so on. This is the basis of recursion. This concept helps to solve many complex problems very easily.

6.1 Definition

In almost every programming language, a function or procedure may invoke other functions or procedures. Not only from other functions, a function may be invoked from within itself as well. When a function is invoked by itself, the function is called a recursive function. And the process is called recursion. Instead of direct invocation, it may happen that the first function invokes the second function and the second function again invokes the first function in turn. This is also recursion. So, we can define recursion as the process where a function is directly or indirectly invoked by itself. Though it is a comparatively more memory consuming process, it is very effective in implementation where the algorithm demands the same repetitive process but use of iteration is difficult.

For example, we can define factorial of n as n! = n * (n-1)!. So, to find the factorial of n we need to calculate factorial of n-1 first. Again, to calculate the factorial of n-1 we need to calculate factorial of n-2, and so on. But this process may not continue indefinitely. Stack will be overflowed in that case. Hence, we must impose some criteria based on which this invocation should be restricted. This is called base criteria or base condition. Thus, every recursive function must have a base condition. In the above example, we may set the base condition as: when the value of n is 0, instead of recursive call it directly returns 1.

Earlier, we discussed dividing the RTL to GDS implementation flow into two parts: logic synthesis and physical design. In this part of the book, we will discuss logic synthesis. In Part IV, we will discuss physical design.

Logic design involves transforming a high-level functional description to a netlist of standard cells and macros. It takes a design from the functional domain to the structural domain. The primary task of logic design is to decide the logic elements that will deliver the required functionality. Additionally, we need to ensure that the design metrics such as area, performance, power, and testability meet the given requirements.

To ensure that the logic design meets the above requirements, we interleave implementation and verification tasks in a design flow. We have arranged implementation and verification-related chapters similarly. However, note that we carry out some of the verification tasks, such as combinational equivalence checking, timing analysis, and power analysis, multiple times in a design flow.

We will explain implementation of the logical design in Chapter 8 (“Modeling Hardware using Verilog”), Chapter 10 (“RTL Synthesis”), Chapter 12 (“Logic Optimization”), Chapter 16 (“Technology Mapping”), Chapter 17 (“Timing-driven Optimization”), and Chapter 19 (“Powerdriven Optimization”). We will discuss verification aspects for a design in Chapter 9 (“Simulationbased Verification”), Chapter 11 (“Formal Verification”), Chapter 14 (“Static Timing Analysis”), and Chapter 18 (“Power Anlaysis”). We will present the information that is used both in implementation and verification in Chapter 13 (“Library”) and Chapter 15 (“Constraints”).

It is worthy to point out that the primary objective of these chapters is to build a foundation for logic design. Therefore, we explain essential concepts and principles governing it. We have attempted to provide explanations not based on any specific logic synthesis tool or proprietary data format. Therefore, a reader can apply these concepts to any tool s/he chooses for logic design. Additionally, note that these chapters build a foundation for logic design. To gain more depth on these topics, we encourage readers to refer to standard textbooks on them. We have provided references to those textbooks at appropriate places in each chapter.

In the previous chapters, we have discussed wafer-level testing that uses automatic test equipment (ATE). It allows a high degree of automation, achieves good fault coverage, and is cost-effective. Therefore, ATE-based testing is popular and widely adopted for industrial designs. However, ATEbased testing has the following drawbacks or limitations:

• 1. It requires expensive ATE. Moreover, it requires sophisticated facilities equipped with an ATE. We cannot perform it outside the production testing environment. However, sometimes testing, diagnosis, and repair become necessary for a chip that is already integrated into a system.

• 2. It employs voluminous test patterns that increase the test time and the cost of testing. Moreover, the number of test patterns increases with the advancement in technology due to increased circuit complexity. Consequently, the cost of testing increases with the advancement in technology.

• 3. We cannot carry out at-speed testing for high-performance integrated circuits (ICs) due to the impedances associated with the probes of an ATE [1]. However, some types of faults, such as delay faults, can only be detected by at-speed tests [2]. It makes ATE-based techniques inadequate in some situations.

Built-in self-test (BIST) is another testing methodology that addresses the above drawbacks and has become quite popular [3–6]. In this chapter, we will discuss BIST in detail.

We can implement BIST in a design in many ways, depending on the design complexity, target test metrics, and allowed overheads. In this chapter, we describe a typical BIST system to elucidate its basic principles.

BASICS

BIST is a testing technique in which we incorporate additional hardware and software in a chip that enables it to self-test. During self-testing, an IC can test its own operation, both functionally and parametrically. The self-testing does not require an external test pattern. Thus, we eliminate the dependence on an ATE. It allows us to carry out BIST-based testing in the field and even after system integration. Additionally, we can perform at-speed testing because no external signal interfacing is required.

In the previous two chapters we have studied about arrays and other in-built data structures like lists, tuples, sets and dictionaries. In this chapter we will discuss another in-built data type/data structure of Python, and that is string. In programming languages, string handling is a very important task and in data structure we will learn about different algorithms for efficient string handling.

5.1 Introduction

A string is a sequence of characters allocated contiguously in memory where the characters may be letters of the alphabet, digits, punctuation marks, white spaces or any other symbols. In Python a string is implemented as an object of the in-built class str. To define a string constant we may use single quotation (‘ ’), double quotation (“ ”) or triple quotation (‘“ ”’). So, ‘India’, “India” and ‘“India”’ – all three are valid string constants in Python. Apart from a normal string, there are two other types of strings. These are escape sequences and raw strings. Like C, C++ and Java programming, Python also supports escape sequences. An escape sequence is the combination of a backslash (\) and another character that together represent a specific meaning escaping from their original meaning when used individually. Table 5.1 shows some escape sequences in Python.

The following example shows the use of escape sequences:

Example 5.1: Example to show the use of escape sequences.

print(“Hello \nClass!!”)

Output:

Hello

Class!!

print(“Hello \tClass!!”)

Output:

Hello Class!!

print(‘Cat\rM’)

Output:

Mat

print(‘Cat\b\bu’)

Output:

Cut

print(“Welcome to the world of \‘Python\’”)

Output:

Welcome to the world of ‘Python’

print(“\”India\” is great.”)

Output:

“India” is great.

If a string is preceded by an ‘r’ or ‘R’, then it is called a raw string. Within a raw string, escape sequence do not work. They behave like a normal character. Consider the following example:

Example 5.2: Example to show the use of raw string.

print(‘Techno\nIndia’)

Output:

Techno

India

print(r‘Techno\nIndia’)

Output:

Techno\nIndia

print(‘Techno\\India’)

Output:

Techno\India

print(R‘Techno\\India’)

Output:

Techno\\India

5.2 Basic String Operations

Strings are immutable in Python. Hence, we cannot modify a string. But we can create a new string after manipulating an old string. We can extract an individual character or portion of a string. Characters within a string are accessed using the subscript operator and the index value.

In this part of the book, we will introduce integrated circuits (ICs) concepts and give a top-level view of the entire VLSI design flow. In the remaining portion of this book, we will discuss each task of the VLSI design flow in detail. We have taken this approach to present the topics because an early introduction to the entire design flow eases building context for individual tasks. It allows us to relate one task with another in the remaining portion of this book. We can appreciate the interaction between them and understand how decisions of one task impact other tasks. As a result, we can easily comprehend challenges and opportunities in optimizations and develop a solid understanding of the entire flow.

In the first chapter (“Foundation”), we will briefly describe the concepts of digital circuits, devices, CMOS inverters, data structures, and algorithms. Since readers would have been exposed to these topics previously, this chapter will serve as a refresher. Additionally, this chapter will be a handy reference if a reader needs to recall some of these concepts. In the second chapter (“Introduction to Integrated Circuits”), we will introduce the concepts related to ICs, their history, fabrication, economics, and figures of merit. In the third (“Pre-RTL Methodologies”) and fourth (“RTL to GDS Implementation Flow”) chapters, we will describe the implementation of a design from concept to the layout. In the fifth (“Verification Techniques”) and sixth (“Testing Techniques”) chapters, we will discuss basic concepts related to the verification and testing of ICs. In the seventh chapter (“Post-GDS processes”), we will explain processes involved in fabricating chips from a given layout.

In this chapter we will discuss an important data structure: a heap. Though there are several variations of this data structure, such as binary heap, d-ary heap, B heap, Fibonacci heap, etc., we will discuss here the most popular heap data structure – the binary heap. In the following sections we will mention heap to indicate the binary heap.

11.1 Definition and Concept

Heap is a very important tree-based data structure. It is widely used in computer science. We can define a heap as a binary tree that has two properties. These are: shape property and order property. By shape property, a heap must be a complete binary tree. By order property, there are two types of heaps. One is max heap and the other is min heap. By default, a heap means it is a max heap. In max heap, the root should be larger than or equal to its children. There is no order in between the children. This is true also for its sub-trees. In min heap the order is the reverse. Here the root is smaller than or equal to any of its children. Thus the root of a max heap always provides the largest element of a list whereas the root of a min heap always provides the smallest element. As a heap is a complete binary tree, its maximum height is O(log2n) where n is the total number of elements. Thus both the insertion of new node and the deletion of an existing node can be done in O(log2n) time. Figure 11.1 shows a max heap and a min heap.

11.2 Representation of a Heap in Memory

Like other data structures, a heap also can be represented in memory using an array (or a list in Python) and a linked list. The main problem in tree representation using arrays is in wastage of memory. But in case of complete binary tree representation, that chance is almost nil. Moreover, we need not waste space for storing references of left and right children. So, using arrays (or lists in Python) we can represent the heap data structure efficiently.

In the previous chapters, we discussed the tasks required for designing an IC. Once we have obtained the final layout, the design process is complete. Subsequently, the GDS file corresponding to the final layout is employed for making a chip using tasks such as mask preparation, wafer fabrication, testing, and packaging. In this book, we have grouped all chip-making tasks carried out after obtaining the GDS file as post-GDS processes.

Though post-GDS processes are not directly related to the design flow, we need to understand them to appreciate the challenges of fabrication, and possibly address some of these challenges during the design phase. Therefore, we briefly explain post-GDS processes in this chapter. For a detailed understanding of post-GDS processes, readers can refer to dedicated books on these topics such as [1–5].

MASK FABRICATION

We have discussed in Chapter 2 (“Introduction to integrated circuits”) that an essential step in IC fabrication technology is photolithography. It involves transferring the patterns in a layout for a given layer to the silicon wafer. We carry out photolithography separately for each layer.

To start with, we create a replica of the pattern of a given layer on a substrate such as glass. This replica of the pattern is known as mask or reticle. After creating a mask, we use it many times for carrying out photolithography during high-volume manufacturing [4].

We can fabricate a mask using several techniques. Nevertheless, a typical mask fabrication flow consists of the following steps:

• 1. Data preparation

• 2. Mask writing and chemical processing

• 3. Quality checks and adding protections

We explain these steps briefly in the following paragraphs.

Data Preparation

First, we prepare the given layout data for mask writing. We translate the GDS-specified mask information to a format comprehended by a mask writing tool. It involves converting complicated polygons to simpler rectangles and trapeziums. This process is popularly known as fracturing. It simplifies the task for the mask writing hardware. Additionally, data preparation involves augmenting the mask data to enhance the resolution. We will describe some of these techniques later in this chapter.

In this chapter, we will discuss some of the basic concepts of design for testability (DFT). First, we will introduce the idea of structural testing and how it is different from functional testing. Then, we will explain fault model and its significance in testing. We will discuss single stuck-at fault model in detail. We will highlight the role of structural testing and the single stuck-at fault model in simplifying testing and making it cost-effective. We will also elucidate the problems of controlling and observing signals in a sequential circuit that are encountered during structural testing.

FUNCTIONAL TESTING VERSUS STRUCTURAL TESTING

Let us assume that we need to test a fabricated circuit that implements a Boolean function with N inputs. We can apply all possible 2N input combinations and check whether the outputs match the corresponding entries in the truth table. This is known as functional testing. However, when N is large (such as 50 or 100), the number of possible input combinations becomes dramatically large, and exhaustive functional testing of a circuit becomes infeasible. Therefore, we employ an alternative testing strategy known as structural testing for testing a fabricated circuit [1].

In structural testing, we test the components or hardware that implements a logic function rather than testing the input–output functionality of the implementation [1]. We can choose components at various abstraction levels such as transistors, switches, logic gates, standard cells, and macros (adders, multipliers, and arithmetic logical units (ALUs)). Nevertheless, we perform structural testing often at the level of logic gates. This testing is known as structural testing since it considers the topology and interconnections of logic gates in the implementation. The paradigm of structural testing is widely employed because it reduces the number of test patterns required for good test quality [2].

If we perform functional testing, we need to apply 216=65536 input combinations and compare the obtained circuit response with the correct response.