…program testing can be a very effective way to show the presence of bugs, but is hopelessly inadequate for showing their absence. The only effective way to raise the confidence level of a program significantly is to give a convincing proof of its correctness…
—Edsger W. Dijkstra, “The humble programmer,” ACM Turing Lecture, 1972
A design undergoes several changes during a design flow. These changes are expected to meet or preserve the specified functionality. Nevertheless, sometimes the design functionality can deviate from the given specification due to various reasons.1 We need to detect and fix these problems as soon as possible.
In general, verification takes considerable manual and computational effort [1–3]. Consequently, various types of verification techniques have evolved over the last few decades with different resource usage, manual intervention requirement, and rigor. Among them, formal verification is more rigorous, typically requires more computational resource, and is now routinely employed in a design flow. In this chapter, we will explain the basics of formal verification techniques.
LIMITATIONS OF SIMULATION-BASED VERIFICATION
The most commonly employed functional verification technique is simulation.2 In this approach, we simulate a design for a set of test vectors and compare the output response with the expected response. If these two responses agree, then the design is considered to be functionally correct.
A simulation-based verification is fast and straightforward. It can efficiently find functional problems in a design and is especially useful for quickly detecting bugs and fixing functional problems in the early phases of design implementation. However, the biggest problem of a simulation-based verification is its non-exhaustiveness. A huge number of test vectors are possible for a given design, and we cannot simulate all of them.
A and B can independently take one of the 232 possible values. Consequently, the number of possible test vectors is 232 × 232 = 264. Simulation time required is 264 × 1 × 10â6 seconds ≈ 0.5 million years.
Thus, simulation-based exhaustive verification is not feasible for real-world designs.
In practice, we simulate a design for a subset of all possible test vectors. Typically, we provide those test vectors that can discover some anticipated bugs.