CHAPTER OVERVIEW

Modern computer systems are becoming increasingly complex as more devices and functionalities are integrated. Throughout the entire design cycle of systems, simulation is a crucial tool for computer architecture researchers to evaluate novel ideas and explore the design space. Compared with hardware prototyping and analytic modeling, simulation strikes a better balance between accuracy, cost, flexibility, and complexity. As the design complexity of state-of-theart microprocessors keeps growing and manufacturing costs skyrocket, computer architecture simulation has become critical.

Simulations are pervasive in computer architecture research and design and affect the productivity of these activities to a great extent. Productivity is impacted at two levels: (1) the time and effort spent on developing the simulator and (2) the time consumed on running simulations with representative benchmarks. The dramatic growth of the integration density of microprocessor chips provides computer architects abundant on-chip real estate to enhance computing power with more complex architectural designs. In addition, power and reliability have turned into critical design constraints. Building a simulation infrastructure that allows a designer to consider performance, power, and reliability in a single unified framework leads to significant cost and delays in simulator development. Another direct consequence of a complex infrastructure is that simulation itself slows down, increasing the turnaround time for each design state exploration. Simulation slowdown is becoming particularly acute as computer architecture moves into the chip multiprocessor (CMP) era. The current approach of simulating CMPs with growing numbers of cores in a single thread is not scalable and cannot be sustained over time.

CHAPTER OVERVIEW

The processor and its instruction set are the fundamental components of any architecture because they drive its functionality. In some sense the processor is the “brain” of a computer system, and therefore understanding how processors work is essential to understanding the workings of a multiprocessor.

This chapter first covers instruction sets, including exceptions. Exceptions, which can be seen as a software extension to the processor instruction set, are an integral component of the instruction set architecture definition and must be adhered to. They impose constraints on processor architecture. Without the need to support exceptions, processors and multiprocessors could be much more efficient but would forgo the flexibility and convenience provided by software extensions to the instruction set in various contexts. A basic instruction set is used throughout the book. This instruction set is broadly inspired by the MIPS instruction set, a rather simple instruction set. We adopt the MIPS instruction set because the fundamental concepts of processor organizations are easier to explain and grasp with simple instruction sets. However, we also explain extensions required for more complex instruction sets, such as the Intel x86, as need arises.

Since this book is about parallel architectures, we do not expose architectures that execute instructions one at a time. Thus the starting point is the 5-stage pipeline, which concurrently processes up to five instructions in every clock cycle. The 5-stage pipeline is a static pipeline in the sense that the order of instruction execution (or the schedule of instruction execution) is dictated by the compiler, an order commonly referred to as the program, thread, or process order, and the hardware makes no attempt to re-order the execution of instructions dynamically.

CHAPTER OVERVIEW

Technology has always played the most important role in the evolution of computer architecture over time and will continue to do so for the foreseeable future. Technological evolution has fostered rapid innovations in chip architecture. We give three examples motivated by performance, power, and reliability. In the past, architectural designs were dictated by performance/cost tradeoffs. Several well-known architectural discoveries resulted from the uneven progress of different technological parameters. For instance, caches were invented during the era when processor speed grew much faster than main memory speed. Recently, power has become a primary design constraint. Since the invention of the microprocessor, the amount of chip realestate has soared relentlessly, enabling an exponential rise of clock frequencies and ever more complex hardware designs. However, as the supply voltage approached its lower limit and power consumption became a primary concern, chip architecture shifted from high-frequency uniprocessor designs to chip multiprocessor architectures in order to contain power growth. This shift from uniprocessor to multiprocessor microarchitectures is a disrupting event caused by the evolution of technology. Finally, for decades processor reliability was a concern primarily for high-end server systems. As transistor feature sizes have shrunk over time they have become more susceptible to transient faults. Hence radiation-hardened architectures have been developed to protect computer systems from single-event upsets causing soft errors.

These examples of the impact of technology on computer design demonstrate that it is critical for a reader of this book to understand the basic technological parameters and features, and their scaling with each process generation.

CHAPTER OVERVIEW

Interconnection networks are an important component of every computer system. Central to the design of a high-performance parallel computer is the elimination of serializing bottlenecks that can cripple the exploitation of parallelism at any level. Instruction-level and thread-level parallelisms across processor cores demand a memory system that can feed the processor with instructions and data at high speed through deep cache memory hierarchies. However, even with a modest miss rate of one percent and with 100 cycle miss penalty, half of the execution time can be spent bringing instructions and data from memory to processors. It is imperative to keep the latency to move instructions and data between main memory and the cache hierarchy short.

It is also important that memory bandwidth be sufficient. If the memory bandwidth is not sufficient, contention among memory requests elongates the memory-access latency, which, in turn, may affect instruction execution time and throughput. For example, consider a nonblocking cache that has N outstanding misses. If the bus connecting the cache to memory can only transfer one block every T cycles, it takes N × T cycles to service the N misses as opposed to T cycles if the bus can transfer N blocks in parallel.

The role of interconnection networks is to transfer information between computer components in general, and between memory and processors in particular. This is important for all parallel computers, whether they are on a single processor chip – a chip multiprocessor or multi-core – or built from multiple processor chips connected to form a large-scale parallel computer.

I have described the aims and approach of my commentary in the Introduction; here it is my pleasure to acknowledge the many debts I have incurred during its long evolution.

My first thanks go to the series editors Philip Hardie and Stephen Oakley, who read the entire manuscript and substantially improved it by their comments. With great generosity Gian Biagio Conte and Richard Thomas read the commentary and offered numerous valuable suggestions and corrections. A portion of the commentary in an earlier form benefited from careful reading by E. J. Kenney and P. E. Easterling.

For advice and information on specific points I am grateful to Ewen Bowie, Cynthia Damon, Carlotta Dionisotti, Katherine Dunbabin, Catharine Edwards, Christian Flow, Albert Henrichs, Tom Jenkins, Jennifer Ledig, Gregory Nagy, Lara Nicolini, Silvia Ottaviano, Sergios Paschalis, Andreola Rossi, Mark Schiefsky, Ben Tipping, and Tony Woodman. Special thanks to Miriam Carlisle for alerting me to the possible relevance of the Tyszkiewicz Painter’s vase (see Appendix).

James Zetzel suggested that I include a section on metre in the Introduction, but he bears no responsibility for its content. Alessandro Schiesaro secured for me a copy of Alfonso Traina’s commentary (a work unfortunately hard to find in this country), and Professor Traina himself kindly sent me a copy of the second edition, containing an updated bibliography. Ian Goh carefully checked references, and Lauren Curtis offered timely assistance in preparing the final form of the commentary.

Kind invitations from various institutions gave me the chance to try out ideas before committing them to print. I mention in particular the Scuola Normale Superiore in Pisa, the Society for the Promotion of Roman Studies in London, Amherst College, Princeton University, Skidmore College, the University of Virginia, and Washington and Lee University. Audiences on those occasions have been most helpful in their comments.

A red-figure calyx crater from c. 470bce in the Museum of Fine Arts in Boston attributedto the Tyszkiewicz Painter shows (a) Diomedes wounding Aeneas (=LIMC s.v. Aineias 38) and (b) Achilles killing Memnon (=LIMC s.v. Achilleus 833). The vase is remarkable for theprominence given to Memnon's shield and its gorgon emblem; it is the only one offive shields on the vase shown facing outward, and Achilles’ gaze appearsto be fixed on it. Memnon's death is an act of retribution for his having killedAchilles’ younger friend Antilochus; it seems at least possible thatMemnon is carrying a shield that reminds Achilles of that event and so heightenshis determination to exact revenge. In several other vase paintings of the duelbetween Achilles and Memnon, a figure on the ground between them is identifiedas Antilochus; on the Boston vase, however, he is named as Melanippus, a Trojankilled by Antilochus (see Il. 15.575–8) before he was inturn killed by Memnon. As well as alluding to a still earlier episode in thechain of events, the introduction of Melanippus (along with, presumably, his ownshield) increases the likelihood that the gorgon shield carried by Memnon is atrophy taken from Antilochus.

1–80 Latinus and Amata fail to dissuade Turnus from meeting Aeneasin single combat

The opening scene begins as a sort of internal monologue of Turnus then developsinto a three-way conversation with Latinus and Amata, with Lavinia in asignificant silent role. The focus, however, remains on T. throughout, as isshown by the arrangement of speeches(Turnus–Latinus–Turnus–Amata–Turnus). The sceneevokes and conflates two primary Iliadic models, the meeting of Hector andAndromache in 6.390–493 and the vain efforts of Priam and Hecuba todissuade Hector from meeting Achilles in 22.25–92. The Homeric echoesalign T. with Hector in the role of the doomed warrior soon to meet his death,thereby undercutting several of his boasts and threats (see 50n.,75–80nn.). The influence of Greek tragedy can be seen in the distributionof speeches and perhaps also in the limitation of speakers to three, which makesLavinia a non-speaking character (a kophon prosopon), see64–9n.

The action presumably takes place inside Latinus’ palace, but the physicalsetting is left remarkably vague; contrast Homer’s circumstantialdescription of the encounter of Hector and Andromache in Il.6.390–406. The transition (at 10) from T.’s opening thoughts tohis first speech is also strikingly fluid. The result is to concentrateattention on the feelings of the characters, especially T., who is made toappear isolated even when in the company of others. On the relative rarity ofconversation in the ‘rigidly undomestic’ Aeneidsee Feeney (1983) 213–14 (= Harrison (1990) 181–2); Johnson (1976)179 comments on ‘the sense of isolated anxiety, bad solitude, which is aVergilian hallmark’.