In Chapter 8, the statistical nature of electromigration is described. Along with understanding of the basic physical degradation mechanisms, this is an important area of research due to the need for extrapolations from simple test structures to the product level. One has to keep in mind that electromigration testing is usually done on single-link structures. In some instances, a few links are stitched together in a series or parallel fashion, but massive-scale studies with large interconnect arrays have not been implemented yet as a standard testing methodology. Only the application of very large test structures with an extended amount of interconnect links encompassing metal lines and contacts/vias can lead to the detection of “early” or “extrinsic” failures, which are the limiting factor in the extrapolation to product-level interconnect systems. The detection of these early failures in electromigration and the complicated statistical nature of this important reliability phenomenon have been difficult issues to treat for decades in the past. In Chapter 8, an innovative technique utilizing large interconnect arrays in conjunction with the well-known Wheatstone Bridge are discussed, and both Al- and Cu-based interconnect technologies are described.

The momentum exchange between lattice atoms and conduction electrons together with the stress gradient along the metal wire embedded into the rigid confinement are two major driving forces for electromigration-induced evolution of stress and vacancy concentration. The growth of mechanical stress causes an evolution of a variety of defects that are inevitably present in the metal, leading to void formation. It affects the electrical properties of the interconnect. In order to estimate the time to failure caused by voiding, the kinetics of stress evolution should be resolved until the first void is nucleated. Then the analysis of the void size evolution should be performed in order to trace changes in resistances of individual voided lines and vias. In this chapter, we review the major results that have been achieved with the 1D phenomenological EM model. We demonstrate its capability to predict the transient and steady-state distributions of the vacancy concentration and the hydrostatic stress, a void nucleation, and its growth, and also a drift of small voids along a metal wire. Despite its simplified nature, the 1D model is capable of addressing the confinement effect of ILD/IMD dielectric on EM-induced degradation, and also the effect of metal grain structure.

A very different picture of the redistribution of metal density and stress, caused by electric stressing, can be expected in multibranch interconnect structures formed by connected metal lines within the same metal layer. The absence of diffusion barriers in line junctions allows atoms to freely migrate between lines along the trajectories of the current carriers. When a multibranch structure includes metal lines that are connected in parallel, the creation of a void in one of the parallel branches does not necessarily result in a failure, which contrasts with what happens in a single line segment, because current can continue to flow in the unvoided parallel lines. The on-chip power/ground (p/g) grid is an example of such electrically redundant multibranch structures. In this chapter, we review a recently developed assessment methodology of the p/g grid MTTF and describe a novel experimental technique that could validate the proposed methodology. EM assessment performed on the grids with tens of millions of nodes has shown that the formation of the first void alone didn’t cause a grid failure. A failure criterion of 10% voltage drop increase was met due to cumulative effect of nucleation of several voids and their growth in the failed branches.

In Chapter 5, we show that the microstructure and interfaces are important in controlling EM reliability of Cu damascene interconnects where the EM lifetime can be significantly improved with metal capping or alloying. In this chapter, we investigate the scaling effect on microstructure and the implication on EM reliability for Cu and Co damascene lines. The scaling effect on Cu microstructure was investigated using a high-resolution electron microdiffraction technique down to 22 nm linewidth for the 14 nm node. The results showed a systematic trend of microstructure evolution in Cu damascene lines with continued scaling. A Monte Carlo simulation was carried out to investigate grain growth in Cu interconnects beyond 22 nm linewidth based on total energy minimization. The simulation results enabled us to understand how the interface energy counteracts the strain and grain boundary energies to control the microstructure evolution in Cu lines with continued scaling. Then the scaling effect on microstructure evolution of Co damascene lines was investigated beyond the 10nm node using both electron microdiffraction and simulation. The simulated microstructures of Cu and Co interconnects are used to project the scaling effect on EM reliability beyond the 10 nm node.

An accurate analysis of the stress evolution in a metal line loaded with an electric current requires solution of a number of coupled partial differential equations (PDEs). The continuity equations, describing the evolution of concentrations of vacancies and plated atoms along the line, are linked with the force balance equation yielding the elastic stress evolution due to interaction of the metal line volumetric deformation with the rigid confinement. The electric current density distribution is found by solving the corresponding Laplace equation. Accounting for the polycrystalline structure of the metals used as conductors in on-chip interconnects, and proper consideration of a variety of venues for diffusion of vacancies, such as grain boundaries and interfaces with liners and capping layers, requires a comprehensive 2D or 3D analysis. Following void nucleation, which happens when the tensile stress reaches a critical value, the void shape and size are described by a combination of the Cahn–Hilliard and Allen–Kahn equations with the phase-field formalism. Detailed description of these coupled PDEs and results of their solution for a number of cases using finite element analysis (FEA) are demonstrated in this chapter. A good fit between simulation results and measurements is demonstrated throughout the chapter.

Scaling on-chip Cu wiring dimensions has degraded electromigration (EM) reliability with the same metallization and rapidly increased Cu resistivity. The size effects in EM and resistivity were caused by increased contributions from EM-induced mass flow and electron scattering with interfaces and grain boundaries, respectively. The EM Cu interconnect lifetime had further degraded by the decrease in the void volume required to cause EM failure. The Cu interconnect resistance was further increased by increasing the volume fraction of barrier/liner in metal wires that were required to produce chips with good reliability. In this chapter, we review the Cu microstructure and resistivity for various CMOS technological nodes, the basic physics of the EM phenomenon addressing EM mass transport, lifetime scaling rule, and damage formation in Cu damascene line structures. This is followed with discussions on Blech short length and EM scaling rule. Several techniques developed for improving EM reliability using upper-level dummy vias, impurities, Cu surface treatments, alternated liners, and surface metal coating are discussed together with the effects of Cu microstructure, atomic layer deposition MnOx liner, and Cu/carbon nanotube composite line on EM.Finally, the EM lifetimes, failure mechanisms and activation energies through various technological nodes are presented.