In this chapter we discuss experiments in cavity QED and ion traps. We first discuss the nature of Rydberg atoms which are used in cavity QED experiments. The experimental realization of the Jaynes––Cummings model is discussed, as are the generation of Schrödinger-cat states in dispersive atom––field interactions in cavity QED. The quantum non-demolition measurement is discussed. The realization of the Jaynes––Cummings model in the context of trapped ions is discussed.

In this chapter we first describe the experiments of Grangier et al., which gave clear evidence of anti-correlation effects and of the interference effects where only a single photon is involved. We then provide a fully quantum mechanical treatment of a lossless beam splitter. Interferometry with single photons is then treated fully quantum mechanically. Interaction-free measurement is then discussed, followed by interferometry with coherent states of light. Next, the SU(2) formulation of beam splitters and interferometers is discussed.

As we have seen throughout this book, material deposition and material removal are critical steps in integrated circuit (IC) fabrication. A wide variety of materials, insulators, semiconductors and conductors must be deposited at various stages in chip manufacturing. Usually, these materials are deposited in blanket form covering the entire wafer surface, although there are some deposition methods which are selective and deposit materials only in specific locations on the wafer surface. We will discuss deposition methods in detail in Chapter 10. Selective removal of material is usually accomplished using a lithography-defined mask followed by etching. We will discuss a variety of etching methods in this chapter.

Material removal can also be accomplished using chemical–mechanical polishing (CMP). This process is usually not selective but uses a combination of chemical etching and mechanical polishing to remove materials. The original motivation for developing CMP was to planarize wafer surfaces in back-end structures, since the polishing produces a flat surface.

Multiple deposited layers make up the core of almost all devices, whether micro-electromechanical systems (MEMS) or semiconductor circuits. Successive layers are deposited, patterned and etched to form the complex stacked structures that provide the desired functionality. The range of deposition techniques used varies widely even if we consider a single specific process, such as building a complementary metal-oxide–semiconductor (CMOS) chip. The toolbox of deposition systems is extensive, providing interesting choices for process designers. To provide some structure to this chapter, we divide deposition systems by their thermal profiles, from high-temperature to low-temperature systems, as this often determines their utility at a particular step in a process. It has the advantage of mimicking the historical development, but process engineers use the entire spectrum of systems from the deposition toolbox to develop a novel process.

Almost from the very beginning, it was clear that silicon was the best choice for the material on which to base the integrated circuit (IC) industry. The abundance of silicon, the availability of simple techniques for refining it and growing single crystals, the essentially ideal properties of the Si/SiO2 interface and the invention of manufacturing techniques based on the planar process, all led to the dominance of silicon-based devices by the early 1960s.

However, while silicon has dominated this $500 billion industry, other semiconductors have found markets where they outperform silicon or do things that silicon simply cannot do. The compound semiconductor market today is worth approximately $15 billion, dominated by GaAs devices that operate at higher frequencies than Si devices. SiC and GaN are opening multi-billion-dollar market opportunities in power devices. Light-emitting diodes (LEDs) for general lighting and other displays are a $15 billion market today.

In the silicon complementary metal-oxide–semiconductor (CMOS) process discussed in Chapter 2, the “back-end” (wiring) portion of the process flow was described (see Figure 11.1(a)) with tungsten (W) vias, two layers of Cu wiring and two layers of deposited dielectric. In the discussion in Chapter 2, perhaps an inkling of the actual complexity of this part of the process was given through the brief discussion of TiN or TaN barrier/adhesion layers, chemical vapor deposition (CVD) of tungsten, chemical–mechanical polishing (CMP) to planarize the W layer, deposition of a copper (Cu) seed layer, followed by a thicker electroplated Cu layer, and a “dual damascene” lithography and etching process to pattern the Cu layers. An actual image of a similar back-end silicon CMOS structure is also shown in Figure 11.1(b).

The interface between a semiconductor and an insulator often determines the viability of the material combination in device structures. Silicon is unique in nature, at least among the semiconductors, for having a robust, reliable oxide that can be grown on its surface. The interface between Si and SiO2 is perhaps the most carefully studied of all material interfaces, and is probably the principal reason why silicon has been the dominant semiconductor material. The fact is that silicon naturally oxidizes in the sense that it can be simply placed in a furnace at high temperature with oxygen or water vapor and one obtains a nice, stable dielectric material that is essentially electrically perfect. This distinguishes silicon from all the other simple column IV semiconductor materials. Germanium can be oxidized, but its oxide is soluble in water, which makes it very hard to do any sort of chemical processing.

Lithography is arguably the most important process step in modern integrated circuit (IC) manufacturing. The ability to print patterns with features as small as 10–20 nm and to place those patterns on a substrate with a precision of a few nanometers is what makes today’s chips possible. Virtually all ICs are manufactured today with deep-ultraviolet (DUV) optical lithography operating with 193 nm photons, the basic process introduced in Figure 1.7.