Introduction

Previous chapters in this book have been devoted to the design of domino logic standard cells and methods to synthesize logic using them. In this chapter we describe some example circuits implemented using different automated domino logic design flows. Since the primary benchmark for synthesizable domino logic is against synthesizable static logic, comparisons are provided between the two. Silicon-measured data is also provided wherever it is available.

Domino integer execution unit

A typical application for high-speed logic is in the execution units of microprocessors. Execution units are the main arithmetic modules in processors, performing integer or floating point arithmetic. In order to understand the speed advantages possible with domino logic, we decided to build a simple integer execution unit. The block has an adder, a shifter, a multiplier, and a bit operations unit. Memory modules interact closely with execution units, to provide data and instructions. For this design two 32-entry, 32-bit wide register files are used in each execution unit. One register file supplies the 32-bit wide data operands that are applied to the datapath modules and stores the result. The other register keeps a simple set of instructions. These instructions allow the data operations to start and stop. They also determine the operations to be performed and the data memory locations to be accessed.

A schematic representation of the execution unit data flow is shown in Figure 5.1. Operation starts via instructions sent from the instruction register file. Each arithmetic function receives operands from the data register file.

The state of digital ASIC design methodologies

Digital ASIC design methodologies are now mature technologies. While EDA tools continue to progress and improve, the basic algorithms on which they are based have been well optimized. In addition, the high-speed needs in an ASIC often tend to be focused on small or medium-sized blocks of logic, while the current focus for EDA tools is on dealing with the massive complexity of systems on-chip. Static logic libraries, like EDA tools, have also improved in the last few years, especially with the introduction of pulse-based flip-flops [1, 2]. Beyond that there does not appear to be very much one can do to improve performance significantly beyond the incremental work of increasing the number of cells and type of libraries provided for the synthesis tool. This is common for many maturing industries, where once the low-hanging fruit has been picked further improvements require considerable effort, often for limited gain.

Before the reader decides to accept the limitations in ASIC design flows with the calm serenity with which it is best to accept the unalterable frailties of the human condition, and other such phenomena, it is perhaps useful to remember that custom designs still remain significantly faster than ASIC implementations in the same process generation [3]. This suggests that there still remains scope for further speed improvements in ASIC flows by using custom design techniques.

Interconnect model reduction has emerged as one crucial operation for circuit analysis in the last decade as a result of the phenomenon of interconnect dominance of advanced VLSI technologies. Because interconnect contributes to a significant portion of the system performance, we have to take into account the coupling effects between subcircuit modules. However, the extraction of the coupling renders many small fragments of parasitics. While the values of the parasitics are small, the number of fragments is huge and this makes the accumulated effect non-negligible. If left untreated, the amount of parasitics can gobble up the memory capacity and consume long CPU time during circuit analysis.

Model reduction transforms a system into a circuit of much smaller size to approximate the behavior of the original description. Many researchers have contributed to the advancement of the techniques and demonstrated drastic reduction of the circuit sizes with satisfactory output responses in published reports. Many of these techniques have also been implemented in software tools for applications. However, it is important for the users to understand the techniques in order to use the package properly. To adopt these approaches, we need to inspect the following features.

1. Efficiency of the reduction: the complexity of the reduction algorithm determines the CPU time of the model reduction. The size of the reduced circuit affects the simulation time.

2. […]

In this chapter, we exploit a new way of passive modeling interconnect circuits by so-called signal waveform shaping. Traditional passive modeling methods try to ensure that the reduced models are strictly passive using passive-preserving model order reduction methods or passivity enforcement optimization methods, as shown in Chapter 2 and Chapter 10. In this chapter, we show that passivity can also be achieved by slightly altering (shaping) the waveforms passing through the reduced models.

Introduction

Many model order reduction (MOR) techniques have been proposed in the past. The most efficient and successful one is based on subspace projection [32, 37, 85, 91, 113], which was pioneered by asymptotic waveform evaluation (AWE) algorithm [91] where explicit moment matching was used to compute dominant poles at low frequencies. After AWE, more numerical stable techniques were proposed [32, 37, 85, 113] by using implicit moment matching and congruence transform to produce passive models. A detailed review of Krylov subspace methods can be found in Chapter 2.

Another important development in linear MOR is the introduction of truncated balanced realization (TBR) methods, where the weak uncontrollable and unobservable state variables are truncated to achieve the reduced models [81, 87, 89, 131]. The TBR methods can produce nearly optimal models but they are more computationally expensive than projection-based methods.

Compact modeling of passive RLC interconnect networks has been an intensive research area in the past decade owing to increasing signal integrity effects and interconnect-dominant delay in current system-on-a-chip (SoC) design [72].

In this chapter, we briefly review the existing modeling order reduction (MOR) algorithms for linear time-invariance (LTI) systems developed over the past two decades in the electrical computer-aided design community. Since compact modeling of TLI systems is a well researched and studied field, many efficient approaches have been proposed over the years. Given the space in this book, we cannot review all of them and neither do we attempt to be complete in our review. Instead, we mainly review the Krylov subspace projection-based model order reduction methods, which are widely used MOR methods and are closely related to the rest of this book. Although there exists an excellent and detailed treatment of Krylov subspace projection-based methods already [14], for the completeness of this book, we still present some basic concepts, algorithms and important results for Krylov subspace projection-based MOR methods. We try to present them in a way that can be easily understood from the practical application point of view.

Moments and moment-matching methods

In this section, we briefly review the concepts of time-domain moments, the Elmore delay and Pade-approximation-based moment-matching method, which are important concepts for subspace projection-based model order reduction methods.

In this chapter, we present some general compact model optimization and passivity enforcement algorithms. Model optimization can be viewed as a fitting-based model generation process, where we fit a parameterized model against the simulated or measured data of original circuits. Model optimization methods can be applied to more general modeling applications like modeling RF and microwave circuits where it is difficult to obtain the models directly from the structures of the circuits. Instead, engineers typically model those circuits by fitting full-wave simulation or measured data. One critical issue in such applications is the preservation of some important circuit properties like passivity and reciprocity.

In this chapter, we introduce some efficient model optimization and passivity enforcement methods, as well as some reciprocity-preserving modeling methods developed in recent years.

Passivity enforcement

In this section, we present the state-space based passivity enforcement method, which is based on the method used in [21], but we will show how this method can be used in the hierarchical model order reduction framework to enforce passivity of the model order reduced admittance matrix Ỹ(s).

Passivity is an important property of many physical systems. Brune [12] has proved that the admittance and impedance matrices of an electrical circuit consisting of an interconnection of a finite number of positive R, positive C, positive L, and transformers are passive if and only if its rational function are positive real (PR).

Introduction

In the chapter, we introduce another structure-preserving model order reduction method, which extends the SPRIM method [37] to more general block forms while the 2q moment-matching property is still preserved. The SPRIM method partitions the state matrix in the MNA (modified nodal analysis) form into natural 2 × 2 block matrices, i.e., conductance, capacitance, inductance, and adjacent matrices. Accordingly, the projection matrix is partitioned. As a result, SPRIM matches twice the moments of the models by using the projection matrix given by PRIMA. The reduced models also preserve the structural properties of the original models like symmetry (reciprocity). This idea has been extended to deal with more partitions by block structure-preserving model order reduction (BSMOR) [136], as shown in Chapter 8 to further exploit the regularity of the many parasitic networks. It was shown that by introducing more partitions, more poles are matched and this leads to more accurate order-reduced models [138].

However, the BSMOR method simply introduce more partitions or blocks; it does not truly preserve the circuit structures for general RLCK circuits for different input sources (voltages or currents). The reduced model does not match the 2q moments of the original models, as SPRIM does.

In this chapter, we first show theoretically that structure-preserving model order reduction can be applied to RLCK admittance networks, which are driven by voltage sources and requires partitioning of the original MNA circuit matrix into 2 × 2 block matrices.

In this chapter, we focus on passive wideband modeling of RLCM circuits. We propose a new passive wideband reduction and realization framework for general passive high-order RLCM circuits. Our method starts with large RLCM circuits, which are extracted by existing geometry extraction tools like FastCap [83] and FastHenry [59] under some relaxation conditions of the full-wave Maxwell equations (like electro-quasi-static for FastCap or magneto-quasi-static for FastHenry) instead of measured or simulated data. It is our ultimate goal that we can obtain the compact models directly from complex interconnect geometry without measurement or full-wave simulations. The method presented in this chapter is called hierarchical model order reduction, HMOR, which is based on the general frequency-domain hierarchical model reduction algorithm [121, 122, 124] and an improved VPEC (vector potential equivalent circuit) [134] model for self and mutual inductance, which can be easily sparsified and is hierarchical-reduction friendly.

The HMOR method achieves passive wideband modeling of RLC circuits via multi-point expension and the convex programming based passivity enforcement method. In this section, we will show that the frequency-domain hierarchical reduction is equivalent to implicit moment-matching around s = 0, and that the existing hierarchical reduction method by one-point expansion [121, 124] is numerically stable for general tree-structured circuits.

Introduction

Model order reduction methods for linear and non-linear dynamic systems in general can be classified into two categories [6]:

1. Singular-value-decomposition (SVD) based approaches

2. Krylov-subspace-based approaches.

Krylov-subspace-based methods have been reviewed in Chapter 2. In this chapter, we focus on the SVD-based reduction methods. Singular value decomposition is based on the lower rank approximation, which is optimal in the 2-norm sense. The quantities for deciding how a given system can be approximated by a lower-rank system are called singular values, which are the square roots of the eigenvalues of the product of the system matrix and its adjoint. The major advantage of SVD-based approaches over Krylov subspace methods lies in their ability to ensure the errors satisfying an a-priori upper bound. Also, SVD-based methods typically lead to optimal or near optimal reduction results as the errors are controlled in a global way. However, SVD-based methods suffer the scalability issue as SVD is a computational intensive process and cannot deal with very large dynamic systems in general. In contrast, Krylov-subspace-based methods can scale to reduce vary large systems due to efficient computation methods for moment vectors and their orthogonal forms.

SVD-based approaches consist of several reduction methods [6]. In this chapter, we mainly focus on the truncated-balanced-realization (TBR) approach and its variants, which were first introduced by Moore [81].

Complexity reduction and compact modeling of interconnect networks have been an intensive research area in the past decade, owing to increasing signal integrity effects and rising electro and magnetic couplings modeled by parasitic capacitors and inductors. Most previous research works mainly focus on the reduction of internal circuitry by various reduction techniques. The most popular one is based on subspace projection [32, 37, 85, 91, 113]. The projection-based method was pioneered by asymptotic waveform evaluation (AWE) algorithm [91], where explicit moment matching was used to compute dominant poles at low frequency. Later on, more numerical stable techniques were proposed [32,37,85,113] by using implicit moment matching and congruence transformation.

However, nearly all existing model order reduction techniques are restricted to suppress the internal nodes of a circuit. Terminal reduction, however, is less investigated for compact modeling of interconnect circuits. Terminal reduction is to reduce the number of terminals of a given circuit under the assumption that some terminals are similar in terms of performance metrics like timing or delays. Such reduction will lead to some accuracy loss. But terminal reduction can lead to more compact models after traditional model order reduction has been applied to the terminal-reduced circuit, as shown in Figure 6.1.

For instance, if we use subspace projection methods like PRIMA [85] for the model order reduction, a smaller terminal count will lead to smaller reduced models, given the same order of block moment requirement for both circuits.

As VLSI technology advances with decreasing feature size as well as increasing operating frequency, inductive effects of on-chip interconnects become increasingly significant in terms of delay variations, degradation of signal integrity, and aggravation of signal crosstalk [72, 116]. Since inductance is defined with respect to the closed current loop, the loop-inductance extraction needs to specify simultaneously both the signal-net current and its returned current. To avoid the difficulty of determining the path of the returned current, the partial element equivalent circuit (PEEC) model [101] can be used, where each conductor forms a virtual loop with infinity and the partial inductance is extracted.

To model inductive interconnects accurately in the high frequency region, RLCM (M here stands for mutual inductance) networks under the PEEC formulation are generated from discretized conductors by volume decomposition according to the skin-depth and longitudinal segmentation according to the wavelength at the maximum operating frequency. The extraction based on this approach [59, 83, 84] has high accuracy but typically results in a huge RLCM network with densely coupled partial inductance matrix L. A dense inductively coupled network sacrifices the sparsity of the circuit matrix and slows down the circuit simulation or makes the simulation infeasible. Because the primary complexity is a result of the dense inductive coupling, efficient yet accurate inductance sparsification becomes a need for extraction and simulation of inductive interconnects in the high-speed circuit design.