Published online by Cambridge University Press: 05 July 2014
Introduction
The mobile devices of the future are expected to be able to communicate with each other wirelessly at ever increasing data rates, and to be able to run a vast number of applications, with a great need for more computational speed and power. Indeed, it is fore seeable that approaching data rates of gigabits per second can alone be a challenge: large bandwidths in the gigahertz range and increased complexity in interference cancelation and error correction coding, combined with cognitive radio and multiple antenna techniques could lead to computing and power consumption needs that are extremely challenging with current conventional methods or any of their expected evolutions. To combat this, there has been a resurgence of interest in application-specific processing, instead of general all-purpose processors. One suggestion for possible future mobile phone architecture is based on the so-called network-on-terminal architecture (NoTA) [74], pictured in Figure 4.1, where different subsystems can be connected via standardized interconnects. Each subsystem consists of computing and memory elements, targeted at specific applications. This will allow more freedom in the design of the subsystem processors, and therefore ease the introduction of novel computing technologies into mobile phones, perhaps some of which could be based on new nanotechnology-enabled computing elements.
Nanocomputing has been attracting a lot of attention since the arrival of efficient tools for nanoscale manipulation of matter. The hope is that the new opportunities provided by nanotechnology will provide faster computation and signal processing systems so that challenging computational problems can be solved more efficiently, possibly using new computational principles.
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