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Ultra thin gate oxide characterization

Published online by Cambridge University Press:  15 July 2004

D. Roy ,
S. Bruyere ,
D. Rideau ,
F. Gilibert ,
L. Giguerre ,
F. Monsieur ,
G. Gouget  and
P. Scheer
D. Roy*
Affiliation:
STMicroelectronics, Central R&D labs, 850 rue Jean Monnet, BP 16, 38926 Crolles, France
S. Bruyere
Affiliation:
STMicroelectronics, Central R&D labs, 850 rue Jean Monnet, BP 16, 38926 Crolles, France
D. Rideau
Affiliation:
STMicroelectronics, Central R&D labs, 850 rue Jean Monnet, BP 16, 38926 Crolles, France
F. Gilibert
Affiliation:
STMicroelectronics, Central R&D labs, 850 rue Jean Monnet, BP 16, 38926 Crolles, France L2MP, IMT Technopole de Château-Gombet, 13451 Marseille, France
L. Giguerre
Affiliation:
Philips semiconductors, Central R&D labs, 850 rue Jean Monnet, BP 16, 38926 Crolles, France
F. Monsieur
Affiliation:
STMicroelectronics, Central R&D labs, 850 rue Jean Monnet, BP 16, 38926 Crolles, France
G. Gouget
Affiliation:
STMicroelectronics, Central R&D labs, 850 rue Jean Monnet, BP 16, 38926 Crolles, France
P. Scheer
Affiliation:
STMicroelectronics, Central R&D labs, 850 rue Jean Monnet, BP 16, 38926 Crolles, France
*
david.roy@st.com
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Abstract

The increase of the gate leakage current of advanced CMOS technologies makes standard electrical characterization methods as C(V) measurement or charge pumping more complex and uncertain. In this paper, and based on C(V) characteristics, main elements that directly affect the electrical measurements of ultra thin MOS devices are clarified. Then, classical parameter extraction techniques are reviewed, pointing out their absolute limitations or giving potential keys of improvement.

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References

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