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Surface Conditioning Issues Related to Patiterning and Etching

Published online by Cambridge University Press:  25 February 2011

S.J. Fonash ,
R.A. Ditizio ,
T. Gu ,
P.I. Mikulan ,
O.O. Awadelkarim ,
R.W. Collins ,
J.F. Rembetski ,
K.A. Reinhardt  and
Y.D. Chan
S.J. Fonash
Affiliation:
Center for Electronic Materials and Processing, The Pennsylvania State University, University Park, PA 16802
R.A. Ditizio
Affiliation:
Center for Electronic Materials and Processing, The Pennsylvania State University, University Park, PA 16802
T. Gu
Affiliation:
Center for Electronic Materials and Processing, The Pennsylvania State University, University Park, PA 16802
P.I. Mikulan
Affiliation:
Center for Electronic Materials and Processing, The Pennsylvania State University, University Park, PA 16802
O.O. Awadelkarim
Affiliation:
Center for Electronic Materials and Processing, The Pennsylvania State University, University Park, PA 16802
R.W. Collins
Affiliation:
Center for Electronic Materials and Processing, The Pennsylvania State University, University Park, PA 16802
J.F. Rembetski
Affiliation:
SEMATECH, on assignment from IBM Corporation, Essex Junction, VT 05452
K.A. Reinhardt
Affiliation:
SEMATECH, on assignment from Advanced Micro Devices, Austin, TX 78741
Y.D. Chan
Affiliation:
SEMATECH, on assignment from Rockwell International, Newport Beach, CA 92606
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Abstract

Surface conditioning issues arising from pattern transfer utilizing plasma etching are discussed. Two situations are considered: one in which an oxide on a silicon substrate is exposed to a plasma etching environment and one in which a silicon substrate is exposed to a plasma etching environment. Both situations can lead to the need for surface conditioning and, in some cases, even 950°C, 30 min. furnace anneals or 1050°C, 26 sec. rapid thermal anneals can fail to restore surface and near-surface properties.

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References

REFERENCES

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