An Interconnect Architecture Optimization (IAO) methodology is proposed. The algorithm makes use of fundamental RLCLL2 relations for wiring delays, as well as predictive 3D interconnect density function histograms with y and x axes of wire length and inverse gate delay. The fundamental RLCLL2 relations determine “maximum” wire lengths as a function of wiring size within the wiring hierarchy; the 3D histogram establishes the pre-physical design allocations of wiring nets within the hierarchy. The decision process begins with the set-asides of wiring for power, clock, and vias, and ends with an optimized number of wiring levels and sizes. Some of the major conclusions of the preliminary analyses are: there are no significant problems with wiring at the lowest level as long as the local wire lengths are appropriately scaled; the MOSFET device may not be able to provide enough current to satisfy the capacitive fanout loads within the future allocations of clock period; and the global wires, despite significant improvements in performance, will continue to provide a design and technology challenge for larger chips and higher frequencies.