Hostname: page-component-54dcc4c588-tfzs5 Total loading time: 0 Render date: 2025-10-03T00:04:01.933Z Has data issue: false hasContentIssue false
  • English
  • Français

Materials Limitations in the Higher Electronic Packaging Levels

Published online by Cambridge University Press:  21 February 2011

C. A. Neugebauer
C. A. Neugebauer*
Affiliation:
General Electric Corporate Research & Development P.O. Box 8, KWC-1605, Schenectady, New York 12301
Get access

Extract

Microminiaturization is desirable for reasons of lower cost, lower volume and weight, higher performance, and higher reliability. Microminiaturization is best achieved by downscaling the feature sizes on the chip itself, and this indeed continues to be the major driving force in the electronics revolution. It is normally cheaper, weighs less, is faster, and is more reliable to put as much of a system's interconnection effort on the chip itself (i.e., packaging level 0). Costs increase steeply for interconnections on the higher levels.

Information

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 108 , 1987 , 13
Copyright
Copyright © Materials Research Society 1988

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

Article purchase

Temporarily unavailable

References

REFERENCES

[1]Saraswat, K.C. and Mahammadi, F., IEEE J. Sol. St. Circuits, SC–17, 275 (1982).Google Scholar
[2]Rossi, F.R. and Straehle, W., Proc. NEPSCON East 87 201 (1987).Google Scholar
[3]Grinberg, J., Nudd, G.R., and Etchells, R.D., IEEE Trans. Computers, C 33, 69 (1984).Google Scholar
[4]Ho, C.W., Chance, D.A., Bajorek, C.H., and Acosta, R.E., IBM J. Res. Develop. 26, 286 (1982).Google Scholar