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Fabrication of Bond and Etch Back Silicon on Insulator Using SiGe-MBE and Selective Etching Techniques

Published online by Cambridge University Press:  22 February 2011

D. Godbey ,
L. Palkuti ,
P. Leonov ,
A. Krist ,
J. Wang ,
M. Twigg ,
H. Hughes  and
K. Hobart
D. Godbey
Affiliation:
Naval Research Laboratory, Electronics Science and Technology Division, Code 6810, Washington, D.C. 20375–5000.
L. Palkuti
Affiliation:
Defense Nuclear Agency/RAEE. Alexandria, VA 22310
P. Leonov
Affiliation:
ARACOR, 425 Lakeside Dr., Sunnyvale, CA 94086.
A. Krist
Affiliation:
Naval Research Laboratory, Electronics Science and Technology Division, Code 6810, Washington, D.C. 20375–5000.
J. Wang
Affiliation:
ARACOR, 425 Lakeside Dr., Sunnyvale, CA 94086.
M. Twigg
Affiliation:
Naval Research Laboratory, Electronics Science and Technology Division, Code 6810, Washington, D.C. 20375–5000.
H. Hughes
Affiliation:
Naval Research Laboratory, Electronics Science and Technology Division, Code 6810, Washington, D.C. 20375–5000.
K. Hobart
Affiliation:
Naval Research Laboratory, Electronics Science and Technology Division, Code 6810, Washington, D.C. 20375–5000.
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Abstract

Undoped thin layer silicon on insulator has been fabricated using wafer bonding and selective etching techniques using an MBE grown Si0.7Ge0.3 layer as an etch stop. Defect free, undoped 200–350 nm silicon layers are routinely fabricated using this procedure. A new selective silicon-germanium etch has been developed that significantly improves the ease of fabrication of the BESOI material.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 220: Symposium B – Silicon Molecular Beam Epitaxy , 1991 , 291
Copyright
Copyright © Materials Research Society 1991

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References

REFERENCES

1. Maszara, W. P. and Goetz, G. and Caviglia, A. and McKitterick, J. B., J. Appl. Phys., 64, 4943, 1988.CrossRefGoogle Scholar
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