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The Effects of Interfaces on C-4 Solder Bump Reliability

Published online by Cambridge University Press:  10 February 2011

Michael J. Sullivan
Michael J. Sullivan*
Affiliation:
Lloyd Technology Associates, Inc., Stow MA 01775
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Abstract

C-4 solder bump technology is used as an interconnect method between microelectronic chips and substrates because of four unique features; excellent electrical performance, large number of connections in area arrays, small size and superb reliability in properly fabricated terminals. C-4 terminals consist of chip metallization (BLM or UBM), solder, substrate metallization and underfill, if needed. The reliability of C-4 interconnections will be described in terms of the physical interfaces in the terminal which include insulator-metal, metal-intermetallic, grain boundary and, if needed, underfill-chip/substrate/solder interfaces. Some of these interfaces are present in the as-deposited materials while others form during the solder reflow operation. Reactive UBM's such as Ti/Cu/Au form layers of intermetallic compounds such as TiCu, TiCu2 and TiCu3 and react with hydrogen ambients to form TiH2. The solder reacts with the UBM copper to form Cu3Sn and Cu6Sn5. The solder also reacts with the substrate metallization (electroless Ni-Au as an example) to form Ni3Sn2 and Ni3Sn4. Reactions with Au also occur with the formation of TiAu4 and AuSn. These reactions can cause problems not because the intermetallics are brittle (intermetallics are relatively brittle compared to the solder but they are also very strong as compared to the solder), but because of the consequences of the reactions such as, stress increase, impurity snowplow, Kirkendall voids and intermetallic spalling. Non-reactive UBM's like Cr/Cu/Au require a “phased” region between the Cr and Cu to achieve mechanical adhesion because of the absence of reaction. Proper control of these reactions will eliminate early fails that are usually planar and occur at reaction interfaces. Long term wear-out will occur during power on-off cycling when creep/fatigue cracks nucleate and grow at the grain boundaries in the solder. If underfill is used, impurity assisted crack growth at underfill to chip/substrate/solder interfaces results in increased strain on the solder and failure. Reliability models for these various failure mechanisms will be discussed as well as methods of eliminating early interfacial failures.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 515: Symposium J – Electronic Packaging Materials Science X , 1998 , 55
Copyright
Copyright © Materials Research Society 1998

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References

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