The impact of technology scaling on the MOS transistor performance is studied over a wide range of dielectric permittivities using two-dimensional (2-D) device simulations. It is found that the device short channel performance is degraded with increase in the dielectric permittivity due to an increase in dielectric physical thickness to channel length ratio. For Kgate greater than Ksi, we observe a substantial coupling between source and drain regions through the gate dielectric. We provide extensive 2-D device simulation results to prove this point. Since much of the coupling between source and drain occurs through the gate dielectric, it is observed that the overlap length is an important parameter for optimizing DC performance in the short channel MOS transistors. The effect of stacked gate dielectric and spacer dielectric on the MOS transistor performance is also studied to substantiate the above observations.