Hostname: page-component-745bb68f8f-f46jp Total loading time: 0 Render date: 2025-02-10T12:27:36.825Z Has data issue: false hasContentIssue false
  • English
  • Français

Effect of Ramp Annealing to Ni Induced Lateral Crystallization of Amorphous Silicon

Published online by Cambridge University Press:  17 March 2011

S. Shivani ,
M.C. Poon ,
M. Chan  and
P.K. Ko
S. Shivani
Affiliation:
Dept. of Electrical and Electronic Engineering, Hong Kong University of Science & Technology,Sai Kung, Hong Kong
M.C. Poon*
Affiliation:
Dept. of Electrical and Electronic Engineering, Hong Kong University of Science & Technology,Sai Kung, Hong Kong
M. Chan
Affiliation:
Dept. of Electrical and Electronic Engineering, Hong Kong University of Science & Technology,Sai Kung, Hong Kong
P.K. Ko
Affiliation:
Dept. of Electrical and Electronic Engineering, Hong Kong University of Science & Technology,Sai Kung, Hong Kong
*
Corresponding author: Tel: (852)2358-7047, Fax:(852)2358-1485, e-mail:eepoon@ee.ust.hk
Get access

Abstract

Nickel Metal-Induced-Lateral-Crystallization (MILC) has been used to enlarge the grain size and improve the quality of (poly-Si) Thin-Film-Transistors (TFTs). However, the MILC temperature is still low and the grain size is still small. The feasibility of forming very large grains (single crystal like) from amorphous silicon (a-Si) by combining MILC with ramp annealing has been studied. It has been found that the grain size after ramp annealing is remarkably enhanced and can reach of the order of several ten's of microns. The velocity of MILC with ramp annealing is faster than that of MILC with isothermal annealing. The grain size becomes maximal at around 625°C/2hrs, and saturates at higher temperatures of 625- 1000°C. The effect of temperature, time and other parameters has also been studied in order to maximize the grain size and quality. MILC with ramp annealing at 625°C can greatly lower the process time and reduce the need of subsequent annealing to enhance the grain size. The new technology can have numerous novel applications such as providing a low cost alternative to form silicon-on-insulator (SOI) substrates and a breakthrough for high performance TFTs and novel multi-layers SOI like devices and circuits.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 609: Symposium A – Amorphous & Heterogeneous Silicon Thin Films – 2000 , 2000 , A9.7
Copyright
Copyright © Materials Research Society 2000

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1. Lee, S.W., Jeon, Y.C. and Joo, S.K., Appl. Phys. Lett. 66 (13), pp.1671–1673 (1995).Google Scholar
2. Lee, S.W., Joo, S.K., IEEE Electron Device Letters 17, No. 4, pp. 160–162 (1996).Google Scholar
3. Jin, Z., Bhat, G. A., Yeung, M., Kwok, H.S. and Wong, M., J. Appl. Phys. 84, No. 1, pp. 194–200 (1998).Google Scholar
4. Bhat, G. A., Jin, Z., Kwok, H. S. and Wong, M., IEEE Electron Device Letters 20, No. 2, pp. 97 (1999).Google Scholar
5. Subramanian, V. and Saraswat, K. C., IEEE Trans. Elecron Devices 45, No.9, pp.1934–1939, 1998.Google Scholar