Hostname: page-component-745bb68f8f-b95js Total loading time: 0 Render date: 2025-02-04T16:39:08.479Z Has data issue: false hasContentIssue false
  • English
  • Français

Effect of Polysilicon Deposition and Thermal Cycling on Thin Oxide Quality

Published online by Cambridge University Press:  28 February 2011

N.R. Wu ,
S. Chiao ,
B. Bhushan ,
T. Batra ,
S.K. Fan ,
P. Pizzo  and
C.Y. Yang
N.R. Wu
Affiliation:
Gould AMI Semiconductor, 3800 Homestead Rd. Santa Clara, CA 95051
S. Chiao
Affiliation:
Gould AMI Semiconductor, 3800 Homestead Rd. Santa Clara, CA 95051
B. Bhushan
Affiliation:
Gould AMI Semiconductor, 3800 Homestead Rd. Santa Clara, CA 95051
T. Batra
Affiliation:
Gould AMI Semiconductor, 3800 Homestead Rd. Santa Clara, CA 95051
S.K. Fan
Affiliation:
Gould AMI Semiconductor, 3800 Homestead Rd. Santa Clara, CA 95051
P. Pizzo
Affiliation:
Materials Engineering Department, San Jose State University, San Jose, CA 95192
C.Y. Yang
Affiliation:
EECS Department, Santa Clara University, Santa Clara, CA 95053
Get access

Abstract

A scaled-down MOS transistor requires high-quality thin gate oxide (∼100 Å) as in tunnel oxide for an EEPROM device. Instead of investigating the lower (SiO2/Si) interface properties, we study the upper (poly-Si/SiO2) interface as affected by poly deposition conditions, phosphorus doping, and thermal cycling. The results show that prolonged or high-temperature heat treatment will degrade thin oxide quality. The initial V-t slope derived from constant-current stressing data is used to assess oxide quality.

Type
Articles
Information
MRS Online Proceedings Library (OPL) , Volume 71: Symposium F – Materials Issues in Silicon Integrated Circuit Processing , 1986 , 513
Copyright
Copyright © Materials Research Society 1986

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

1. Sze, S.M., Physics of Semiconductor Devices, 2nd ed. (Wiley, New York, 1981).Google Scholar
2. Grove, A.S., Physics and Technology of Semiconductor Devices (Wiley, 1967).Google Scholar
3. Nicollian, E.H. and Brews, J.R., MOS Physics and Technology (Wiley, New York, 1982).Google Scholar
4. Liang, M.S., Choi, J.Y., Ko, P.K., and Hu, C., IEDM Tech. Digest 1984, 152.Google Scholar
5. Euzent, B., Boruta, N., Lee, J., and Jenq, C. S., IEEE/Proc. IRPS, 1981, 11.Google Scholar
6. Wolters, D.R., Schoot, J.J. van der, and Poorter, T., in Insulating Films on Semiconductors, edited by Verweij, J.F. and Wolters, D.R. (North-Holland, 1983), p. 256.Google Scholar
7. Schoot, J.J. van der and Wolters, D.R.,Insulating Films on Semiconductors., p. 270.Google Scholar
8. Harari, E., J. Appl. Phys. 49, 2478 (1978).CrossRefGoogle Scholar
9. Liang, M.S., IEDM Tech. Digest 1981, 396.Google Scholar
10. Wu, N.R., Chiao, S., Wang, C., Bhushan, B., and Yang, C.Y., MRS Symp. Proc. 47, 99 (1985).CrossRefGoogle Scholar
11. Jenq, C.S., Ranganath, T.R., Huang, C.H., Jones, H.S., and Chang, T.L., IEDM Tech Digest 1981, 388.Google Scholar
12. De, R.F. Keersmaecker, DiMaria, D.J., and Pantelides, S.T., in Physics of SiO and its Interfaces, edited by Pantelides, S.T. (Pergamon, New York, 1978), 189.Google Scholar