Published online by Cambridge University Press: 01 February 2011
We have fabricated and characterized Pt (60nm) / (Sr,Sm)0.8Bi2.2Ta2O9 (SSBT, 130nm) / Pt (60nm) / Ti (10nm) / SiO2 (10nm) / p-Si (MFMIS:metal-ferroelectric-metal-insulator-semiconductor) structure FETs. The area ratio, the ratio of SSBT capacitor area to SiO2 capacitor, is varied from 1 to 15 in the MFMIS-FETs. It is demonstrated that MFMIS-FETs with area ratio of 6 have memory window of 0.5V with supply voltage of 5 V. Dependence of memory window on the area ratio is discussed.
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