Hostname: page-component-745bb68f8f-g4j75 Total loading time: 0 Render date: 2025-02-04T16:47:40.218Z Has data issue: false hasContentIssue false
  • English
  • Français

Self-Consistent Mosfet Tunneling Simulations—Trends in the Gate and Substrate Currents and the Drain-Current Turnaround Effect with Oxide Scaling

Published online by Cambridge University Press:  10 February 2011

H. Z. Massoud ,
J. P. Shiely  and
A. Shanware
H. Z. Massoud
Affiliation:
Semiconductor Research Laboratory, Department of Electrical and Computer Engineering, Duke University, Durham, NC, 27708-0291
J. P. Shiely
Affiliation:
Semiconductor Research Laboratory, Department of Electrical and Computer Engineering, Duke University, Durham, NC, 27708-0291
A. Shanware
Affiliation:
Semiconductor Research Laboratory, Department of Electrical and Computer Engineering, Duke University, Durham, NC, 27708-0291
Get access

Abstract

This paper discusses the simulation needs of deep-submicron MOSFETs beyond the 100 nm technology generation where the tunneling of carriers through the gate dielectric will become a vital issue in device design, optimization, and characterization. We present simulation results of Tunnel-PISCES, a MOSFET device simulator where tunneling in the gate dielectric is implemented in a self-consistent manner with the device equations in the substrate. Simulation results of trends in the gate, substrate, and drain currents with oxide scaling are presented. The drain-current turnaround effect is explained by considering the role of the voltage drop across the polysilicon gate resistance in determining the device gate tunneling conditions.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 567: Symposium R – Ultrathin SiO2 and Higg-K Materials for ULSI Gate Dielectrics , 1999 , 227
Copyright
Copyright © Materials Research Society 1999

Access options

Get access to the full version of this content by using one of the access options below. (Log in options will check for institutional or personal access. Content may require purchase if you do not have access.)

References

REFERENCES

1 National Technology Roadmap for Semiconductors 1997, Semiconductor Industry Association.Google Scholar
2 Taur, Y. and Nowack, R., IEDM 1997.Google Scholar
3 Simmons, J., J. Appl. Phys., 34, 1793 (1963).10.1063/1.1702682Google Scholar
4 Momose, H. et al., IEEE TED, 43, 1233 (1996).Google Scholar
5 Hauser, J. R. and Ahmed, K., p. 235, International Conference on Characterization and Metrology for ULSI Technology - 1998, Edited by Seiler, D. G., Diebold, A. C., Bullis, W. M., Shaffner, T. J., McDonald, R., and Walters, E. J., American Institute of Physics, 1998.10.1063/1.56801Google Scholar
6 Timp, G., et a]., IEDM 1997.Google Scholar
7 Shanware, A. et al., IEEE Electron Device Letters, submitted for publication.Google Scholar